Embodiments of the present invention relate to a semiconductor device in which a polysilicon layer of a lower electrode contact plug is removed by a strip process such that the deposition area of a dielectric film is increased and capacitance of a capacitor is guaranteed, and a method for manufacturing the same.
In case of a semiconductor device such as a Dynamic Random Access Memory (DRAM), it is necessary to reduce the area occupied by the semiconductor device in proportion to the increasing integration degree, and necessary electrostatic capacitance needs to be maintained or increased. Generally, there are a variety of methods to guarantee sufficient cell electrostatic capacitance within a limited area, for example, a method for using a high dielectric material as a dielectric film, a method for reducing a thickness of the dielectric film, a method for increasing an effective region of a lower electrode, etc. Specifically, the method for using the high dielectric material requires time and material investment, for example, the introduction of new equipments or installations, the necessity of verifying the reliability and productivity of a dielectric film, low-temperature processing of a subsequent process, etc. Accordingly, the method for increasing the effective region may offer a benefit in that a conventional dielectric film can be continuously used and the implementation of a fabrication process becomes relatively easier, so that it has been widely used in the actual fabrication process due to the above-mentioned advantages.
There are a variety of methods to increase an effective region of the lower electrode, for example, a method for configuring a lower electrode in the form of a three-dimensional (3D) structure (such as a cylinder or a fin), a method for growing a Hemi Spherical Grain (HSG) on a lower electrode, a method for increasing the height of a lower electrode, etc. Specifically, the method for growing the HSG may cause unexpected problems in guaranteeing Critical Dimension (CD) of at least predetermined level between lower electrodes, and may cause a bridge between lower electrodes due to infrequent HSG desquamation, so that it is difficult for the aforementioned HSG growing method to be applied to a semiconductor device based on the design rule of 0.14 μm or less. Therefore, in general, in order to increase cell electrostatic capacitance, a variety of methods for configuring a lower electrode in the form of a 3D structure and increasing the height of the lower electrode have been widely used. A representative example of such methods is a method for forming a cylindrical lower electrode or a stack-shaped lower electrode.
Specifically, the conventional method for forming the cylindrical lower electrode may remove a sacrificial insulation film from a peripheral part of the lower electrode, and deposit a dielectric film over the lower electrode. In this case, the dielectric material contained in the dielectric film is deposited not only over an inner wall of the lower electrode but also between neighbor lower electrodes, such that all the cells can share a dielectric material and an upper electrode formed over the dielectric material. Provided that the cells share and use such a dielectric material, capacitance (storage capacitance) among all the lower electrodes may be deteriorated or distorted.
As described above, in order to maximize cell capacitance for improving refresh characteristics of the conventional cylindrical lower electrode, the height of each lower electrode can be increased and the spacing between lower electrode contact plugs can be smaller. As a result, a bridge occurs between lower electrodes, making difficult to couple the lower electrode contact plug to the lower electrode.